Many different types memory exist to store data for computers and the like. For example, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), read only memory (ROM), programmable read only memory (PROM), electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash memory are all presently available to provide for data storage.
Each type of memory has its own particular advantages and disadvantages. For example, DRAM and SRAM allow individual bits of data to be erased one at a time, but such memory loses its data when power is removed. Alternatively, EEPROM can be easily erased without extra exterior equipment, but has reduced data storage density, lower speed, and higher cost. EPROM, in contrast, is less expensive and has greater density but lacks erasability.
Flash memory, has become a popular type of memory because it combines the advantages of the high density and low cost of EPROM with the electrical erasability of EEPROM. Flash memory can be rewritten and can hold its contents without power, and thus is nonvolatile. It is used in many portable electronic products, such as cell phones, portable computers, voice recorders, etc. as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc.
As with other types of memory, flash memory is generally constructed of many memory cells that may store binary pieces of information referred to as bits. The respective memory cells are typically comprised of a semiconductor structure, such as a stacked gate metal oxide semiconductor (MOS) transistor device. The memory cells are generally organized into addressable units or groups, which are accessible for read, write and/or erase operations. The cells are, for example, commonly organized into bytes which comprise eight cells, and words which may include sixteen or more cells, usually configured in multiples of eight. The erase, write and/or read operations are commonly performed by application of appropriate voltages to certain terminals of the memory cells. In an erase or write operation, for example, the voltages are applied to cause charge to be removed or stored in a memory cell. In a read operation, on the other hand, appropriate voltages are applied so as to cause a current to flow in the cell, where the amount of current is a function of the amount of charge stored within the cell, among other things. The amount of charge stored within the cell corresponds to a state of the cell, and the state of the cell can be designated for data storage. For example, a certain amount of charge can correspond to a high data state which can be designated as a logic high or a binary data bit “1”. Similarly, a lesser amount of stored charge can correspond to a low state which can be designated as a logic low or a binary data bit “0”. A length of memory cells containing such respective binary bits can be strung together to store data, such as an 8 bit word, for example.
A relatively modern memory technology is dual sided ONO flash memory, which allows multiple bits to be stored in a single cell. In this technology, a memory cell is essentially split into two identical (dualed) parts, each of which is designed to store one of two independent bits. Each dual sided ONO flash memory cell, like a traditional cell, has a gate with a source and a drain. However, unlike a traditional stacked gate cell in which the source is always connected to an electrical source and the drain is always connected to an electrical drain, the source and drain of a dual sided ONO flash memory cells can be reversed depending upon which of the two bits/sides of the memory cell are operated upon.
As with arrays of other types of memory cells, dual sided ONO flash memory cells are fashioned by initially forming conductive bitlines within a semiconductor substrate. However, rather than merely forming an oxide layer over the bitlines in establishing the transistors that serve as the memory cells, a trilayer of oxide nitride oxide (ONO) materials is then formed over the bitlines and substrate in forming an array of ONO flash memory cells. This trilayer of material can be referred to as a “charge trapping dielectric layer”, and generally includes a first insulating layer, a charge trapping layer, and a second insulating layer, where respective amounts of charge can be “trapped” within the charge trapping layer. Wordlines are then formed over the charge trapping dielectric layer substantially perpendicularly to the bitlines. Control over two bits per cell is governed by application of voltage signals to the wordline, which acts as a control gate, and changing bitline connections such that one bit is acted upon when the source and drain are connected in one arrangement and a complementary bit is acted upon when the source and drain are connected in another arrangement. A fixed ground line is generally not necessary in an array of ONO cells due to the differing bitline connections and resulting source and drain arrangements in the cells. As such, an array of ONO cells can be said to embody a “virtual ground” architecture.
A continuing trend in the electronics industry is to scale down electronic devices to produce smaller, yet more powerful devices (e.g., cell phones, digital cameras, etc.) that can perform a greater number of increasingly complex functions faster and with less power. To achieve this, semiconductors and integrated circuits (e.g., memory cells, transistors, etc.) utilized in these devices are continually reduced in size. The ability to “pack” more of these components onto a single semiconductor substrate, or a portion thereof (known as a die), also improves fabrication efficiency and yields. Accordingly, there are ongoing efforts to, among other things, increase the number of memory cells that can be fabricated onto an individual semiconductor wafer (or die).
One technique to pack more memory cells/transistors into a smaller area is to form their structures and component elements closer together. Forming bitlines closer together, for example, shortens the length of a channel defined there-between and allows more devices to be formed in the same area. This can, however, cause certain undesirable phenomena to become more prevalent. For example, isolating two bits or charges stored within a charge trapping layer becomes increasingly difficult as the channel length is decreased and the individual bits are brought closer together within the charge trapping layer. For example, the stored charges can contaminate or interfere with one another as they are brought closer together. This can, for example, cause a current developed in a memory cell during a read operation to seem inordinately high, which can lead to a mistaken interpretation of a logic high or “1” when, in fact, the read should have yielded a logic low or “0”. The fact that stored charges or dual bits can impact one another is sometimes referred to complimentary bit disturb or CBD. Such “mis-reads” can also be exacerbated by parasitic effects that can be experienced when reading a memory cell, as well as by current leakage that may occur in a “virtual ground” type architecture. Accordingly, it would be desirable to be able to read a memory cell, including a dual bit memory cell, in a manner that accounts for these issues and thereby promotes a more accurate read.